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This is a diploma thesis from McGill university implementing an FPGA chess move generator for a chess playing program resembling Deep Blue's specialized ASICs.
This thesis details the use of a programmable logic device to increase the playing strength of a chess program. The time-consuming task of generating chess moves
is relegated to hardware in order to increase the processing speed of the search algorithm. A simpler inter-square connection protocol reduces the number of wires
between chess squares, when compared to the DEEP BLUE design. With this interconnection scheme, special chess moyes are easily resolved. Furthermore, dynamically
programmable arbiters are introduced for optimal move ordering. Arbiter centrality is also shown to improve move ordering, thereby creating smaller search trees. The
move generator is designed to allow the integration of crucial move ordering heuristics. With its new hardware move generator, the chess program's playing ability is
noticeably improved.

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